Dynamic Random Access Memory (DRAM) chips are used to store instructions and data that are used by processors to perform operations in computer systems. In a typical computer system, a processor, such as a microprocessor, communicates with a memory controller that reads and writes the DRAM cells of one or more DRAM chips in order to retrieve information stored in the DRAM chips and store information in the DRAM chips.
DRAM technology is continuously evolving in ways that increase the storage density of the DRAM chips, decrease the latency associated with writing and reading the DRAM chips, increase the bandwidth associated with memory accesses, decrease the power consumption of the DRAM chips, decrease the weight and form factor of the DRAM chips, and decrease the costs of the DRAM chips.
Joint Electron Devices Engineering Council (JEDEC) is a trade and standardization organization that develops standards for semiconductor devices, including DRAM chips. Over the years, JEDEC has developed many standards for DRAM chips including various double data rate (DDR) standards that improve performance, decrease power consumption, and improve packaging.
Recently, JEDEC developed a DRAM standard for a technology known as Wide I/O, which purportedly is a breakthrough technology that will greatly improve performance, bandwidth, latency, power consumption, packaging, and form factor. The Wide I/O standard calls for stacking DRAM chips and using Through-Silicon Via (STV) technology to interconnect the SDRAM chips with each other and with logic on which the chips are stacked. The resulting memory stack has a 512-bit wide interface.
While the proposed Wide I/O stacked configuration has many advantages, it also has some disadvantages. The logic on which the DRAM chips are stacked comprises a system on a chip (SOC). The SOC generates a relatively large amount of heat that needs to be dissipated so that its performance is not detrimentally impacted. With current Wide I/O proposals, the heat sink structure is disposed on top of the uppermost DRAM chip of the stack. In such cases, the DRAM chips will act as insulators that prevent heat from being efficiently conducted from the SOC into the heat sink structure.
A need exists for a memory system that utilizes certain features of Wide I/O in order to obtain the associated benefits, but that also overcomes the aforementioned heat dissipation problems.